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AD5398
AC SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance R
L
= 25 Ω connected to V
DD
, unless otherwise noted.
Table 2.
B Version
1, 2
Parameter
Min
Typ
Output Current Settling Time
250
Rev. A | Page 4 of 16
Unit
μs
Test Conditions/Comments
V
DD
= 5 V, R
L
= 25 Ω, L
L
= 680 μH
scale to scale change (0x100 to 0x300)
1 LSB change around major carry
Max
Slew Rate
Major Code Change Glitch Impulse
Digital Feedthrough
3
0.3
0.15
0.06
mA/μs
nA-s
nA-s
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design and characterization; not production tested.
3
See the Terminology section.
TIMING SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
B Version
Parameter
1
Limit at T
MIN
, T
MAX
f
SCL
400
t
1
2.5
t
2
0.6
t
3
1.3
t
4
0.6
t
5
100
t
62
0.9
0
t
7
0.6
t
8
0.6
t
9
1.3
t
10
300
0
t
11
250
300
20 + 0.1 C
b3
C
b
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD,STA
, start/repeated start condition hold time
t
SU,DAT
, data setup time
t
HD,DAT
, data hold time
t
SU,STA
, setup time for repeated start
t
SU,STO
, stop condition setup time
t
BUF
, bus free time between a stop condition and a start condition
t
R,
rise time of both SCL and SDA when receiving
May be CMOS driven
t
F
, fall time of SDA when receiving
t
F
, fall time of both SCL and SDA when transmitting
Capacitive load for each bus line
1
Guaranteed by design and characterization; not production tested.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH MIN
of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
3
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
are measured between 0.3 V
DD
and 0.7 V
DD.
0
SDA
t
9
SCL
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
1
t
8
CSTART
RSTART
CONDITION
CSTOP
Figure 2. 2-Wire Serial Interface Timing Diagram
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